System for converting states of DMA requests into first serial i

Details System for converting states of DMA requests into first serial i System for converting states of DMA requests into first serial i

1996-08-09

1999-08-10

Lee, Thomas C.

395839, 395292, G06F 1316

Patent

active

059372060

ABSTRACT:
A DS-PCI/ISA bridge device for controlling I/O devices on an external PCI bus and an external ISA bus has the two operation states of proceed and freeze. When the DS-PCI/ISA bridge device receives a serial GNT# from a DMAC core, the operation state is switched from proceed to freeze. In the freeze state, a serial REQ# cycle is only executed when a change has occurred in the state of a DMA request of the I/O device which the DACK# has notified. Execution of serial REQ# cycles for reporting state changes in DMA requests relating to other I/O devices is frozen. Further, the DMAC core is notified whether or not an initiated serial transfer cycle is a cycle for notifying that the DMA request from an I/O device for which notification of DMA cycle execution has been given is inactive, according to the length of the inactive time period of a serial REQ# from the I/O devices. Moreover, the DMAC core transmits by a serial transfer cycle utilizing a serial GNT#, not only serial information for specifying DMA channels for which DMA cycles are executed, but also mode information for indicating whether the DMA channels are set up in cascade mode. If a DMA channel for which a DMA cycle is executed is in the cascade mode, subsequent bus cycles are executed by a bus master.

REFERENCES:
patent: 4897786 (1990-01-01), Pimm et al.
patent: 5123092 (1992-06-01), Buxton et al.
patent: 5396602 (1995-03-01), Amini et al.
patent: 5398243 (1995-03-01), Aguilhon et al.
patent: 5418914 (1995-05-01), Heil et al.
patent: 5450551 (1995-09-01), Amini et al.
patent: 5546587 (1996-08-01), Silver
patent: 5574869 (1996-11-01), Young et al.
patent: 5581782 (1996-12-01), Sarangdhar et al.
patent: 5619661 (1997-04-01), Crews et al.
patent: 5640520 (1997-06-01), Tetrick
patent: 5729762 (1998-03-01), Kardach et al.
PCI Local Bus Specification, PCI Special Intrest Group, Revision 2.1 (1995).
PCI Local Bus Specification, PCI Special Interest Group, Revision 2.1, Jun. 1, 1995.
"82C37A-5 CHMOS High Performance Programmable DMA Controller," Intel: Peripheral Components, 1993, pp. 3-33 to 3-50.
Mobile PC/PCI DMA Arbitration and Protocols: MHPG Architecture Functional Architecture Specification, Intel Corporation, Revision 2.2, Apr. 22, 1996 .

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