Self-aligned metallization for semiconductor device and process

Details Self-aligned metallization for semiconductor device and process Self-aligned metallization for semiconductor device and process

1988-12-08

1990-06-26

James, Andrew J.

Fishing, trapping, and vermin destroying

357 2, 357 59, 437192, 437200, H01L 21283

Patent

active

049376578

ABSTRACT:
A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.

REFERENCES:
patent: 4648175 (1987-03-01), Metz
patent: 4720908 (1988-01-01), Wills
Morosanu and Soltuz, "Kinetics & Properties of Chemically Vapour-Deposited & Tungsten . . . ,"Thin Solid Films, vol. 52, 1978, 181-194.

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