Output buffer with enhanced electrostatic discharge protection

Details Output buffer with enhanced electrostatic discharge protection Output buffer with enhanced electrostatic discharge protection

1990-07-10

1991-10-22

Jackson, Jr., Jerome

357 42, 357 13, 357 2314, H01L 2978, H01L 2940

Patent

active

050600370

ABSTRACT:
A CMOS output buffer is disclosed, which provides ESD protection by incorporating a low resistance path within the p-channel pull-up device. Output buffers according to the prior art can be damaged by ESD occurring at the output terminal having a positive polarity, as the drain-to-substrate diode of the pull-down transistor breaks down in the reverse-bias direction, especially when second breakdown occurs. The p-channel pull-up device, formed within an n-well, is fabricated to have n-type diffusions disposed near to the p-type drain diffusions. The distance between the n-type diffusion and the drain diffusions in the pull-up device reduces the series "on" resistance of the drain-to-n-well diode of the pull-up device, to a level which keeps the voltage at the output terminal below the reverse-bias breakdown voltage of the drain-to-substrate diode in the pull-down device. The pull-up device may be constructed in a ladder structure to facillitate the reduction of this resistance. A further embodiment of the invention is disclosed which provides the same protection to the n-channel pull-down device, by way of an n-well diode with low series resistance, for open-drain or other pull-up configurations.

REFERENCES:
patent: 3821781 (1974-06-01), Chang et al.
patent: 4062039 (1977-12-01), Nishimura
patent: 4616243 (1986-10-01), Minato et al.
patent: 4626882 (1986-12-01), Cottrell et al.

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