Patent
1992-10-23
1994-09-13
Herndon, Heather R.
395400, G06F 1500
Patent
active
053476360
ABSTRACT:
A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.
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Miki Yoshiyuki
Ooi Yasushi
Herndon Heather R.
NEC Corporation
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