Preventing corruption in a multiple processor computer system du

Details Preventing corruption in a multiple processor computer system du Preventing corruption in a multiple processor computer system du

1996-12-17

1999-02-02

Auve, Glenn A.

395284, 395309, G06F 1300

Patent

active

058677283

ABSTRACT:
To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.

REFERENCES:
patent: 5379384 (1995-01-01), Solomon
patent: 5428748 (1995-06-01), Davidson et al.
patent: 5548782 (1996-08-01), Michael et al.
patent: 5568619 (1996-10-01), Blackledge et al.
patent: 5574869 (1996-11-01), Young et al.
patent: 5737524 (1998-04-01), Cohen et al.

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