Patent
1993-06-21
1999-02-02
Meky, Moustafa M.
G06F 1502
Patent
active
058677275
ABSTRACT:
Data is transferred via FIFO memories on a word unit basis. The FIFO memory is designated by an upper bit portion of a write address. An ID bit indicating whether a transfer word indicates a command or parameters is allocated to a lower bit portion and is written into the FIFO memory together with inherent word data. Upon reading, a lower bit portion of a read address is compared with the ID bit read out from the FIFO memory. When they don't coincide, the presence of an error is decided. In case of adding redundant bits to the transfer word and judging a loss of word, on the transmission side, transmission side judgment bits having a fixed bit arrangement 01 of two bits are added to each word. Further, with respect to the m-th word, the transmission side judgment bits are shifted by (m-1) bits and a bit arrangement is changed and the resultant data is transmitted. On the reception side, the transmission side judgment bits are reversely shifted to the original positions and three bits in which one bit adjacent to the transmission side judgment bits was added thereto are checked. When a bit arrangement of the reception side judgment bits corresponding to the transmission side judgment bits coincides with a bit arrangement of the transmission side judgment bits, it is determined that there is no word loss. When they don't coincide, it is decided that there is a word loss.
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patent: 4484272 (1984-11-01), Green
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Treatise presented in Autumn 1992 Meeting of Institute of Electronics and Communication Engineers of Japan, High Speed, Performance Three-Dimensional CG System, Subaru, 7 pages.
Treatise in Nikkei Electronics, Apr. 4, 1993 (No. 578), pp. 148-154.
Fujitsu Limited
Meky Moustafa M.
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