Digital signal processing apparatus

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G06F 1500

Patent

active

053474805

ABSTRACT:
An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The address bus system of the apparatus is connected to the parallel-connected components and conveys instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.

REFERENCES:
patent: 4507728 (1985-03-01), Sakamoto et al.
patent: 4682302 (1987-07-01), Williams
patent: 5053631 (1991-10-01), Perlman et al.

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