Patent
1995-07-25
1998-08-18
Sheikh, Ayaz R.
395733, 395736, 395739, G06F 946, G06F 1314
Patent
active
057970211
ABSTRACT:
An INTC and a CPU are interconnected via a bus. A first line through which an interrupt request signal is transferred to the CPU from the INTC, and a second line through which an interrupt reception signal is transferred from the CPU to the INTC. The INTC outputs both of a vector address and an interrupt mode signal to a bus in response to the interrupt reception signal. The CPU receives the vector address and the interrupt mode signal and carries out the interrupt processing on the basis of these signals. In this way, since the INTC outputs both the vector address and the interrupt processing mode signal by using the bus, it is possible to reduce a number of terminals for connecting the CPU and the INTC with each other.
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R. Jigour, "Using the 3259A Programmable Interrupt Controller", Microsystem Components Handbook, Intel Corporation (1985).
NEC Corporation
Phan Raymond N.
Sheikh Ayaz R.
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