Patent
1995-07-14
1998-08-18
Lall, Parshotam S.
395561, 395568, 395584, 395881, 395733, 395739, G06F 1200
Patent
active
057969965
ABSTRACT:
In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer, thereby completing the write instruction. Prior to executing a read instruction subsequent to the write instruction, the write address and the write data of the output buffer are transferred to a sync buffer and are stored into a write address holding register and a write data holding register. Further, a using state display register is set into the holding state. When the CPU executes the read instruction, the write data of the write data holding register is written into the memory mapped register and the end of the writing operation is synchronized with the end of the read instruction. When the sync buffer unit receives an interruption instruction in the holding state, an interruption return instruction address is returned to an address of the write instruction of the data in the holding state. The process is restarted from the write instruction of the memory mapped register by the control program by the end of the interruption.
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Funaki Jun
Temma Shoji
Barot Bharat
Fujitsu Limited
Lall Parshotam S.
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