Reducing cache snooping overhead in a multilevel cache system wi

Details Reducing cache snooping overhead in a multilevel cache system wi Reducing cache snooping overhead in a multilevel cache system wi

1996-02-22

1998-08-18

Swann, Tod R.

395473, G06F 1200

Patent

active

057969809

ABSTRACT:
A memory system for reducing cache snooping overhead for a two level cache system with multiple bus masters, has a level 2 cache connected to a main memory and a level 1 cache connected to a bus master. Each bus master has one level 1 cache assigned to it. A shared level 2 cache is connected to each of the level 1 caches. The level 2 cache has an inclusion field for each storage location within the level 2 cache. The inclusion field indicates if information held in a storage location associated with the inclusion field is contained in any of the level 1 caches connected to the shared level 2 cache, and whether that data has been modified. If there is a cache hit in the level 2 cache, the level 2 cache determines from the inclusion field that corresponds to the cache hit if the tag-address corresponding to the memory access of the bus master also resides in a level 1 cache assigned to a different bus master than the one that made the memory access, and if the corresponding data has been modified. If so, the shared level 2 cache obtains the data from the level 1 cache assigned to the other bus master, and that data is read into the level 2 cache. The data is then read from the shared level 2 cache into the level 1 cache assigned to the bus master that initiated the memory access.

REFERENCES:
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 5058006 (1991-10-01), Durdan et al.
patent: 5136700 (1992-08-01), Thacker
patent: 5197139 (1993-03-01), Emma et al.
patent: 5249284 (1993-09-01), Kass et al.
patent: 5265232 (1993-11-01), Gannon et al.
patent: 5297269 (1994-03-01), Donaldson et al.
patent: 5369753 (1994-11-01), Tipley
patent: 5530832 (1996-06-01), So et al.
patent: 5564035 (1996-10-01), Lai
patent: 5584013 (1996-12-01), Cheong et al.
"Extended L2 Directory for L1 Residence Recording", IBM Technical Disclosure, vol.34, No.8, pp. 130-133, Jan. 1992.
Baer, Jean-Loup and Wang, Wen-Hann, "On The Inclusion Properties For Mult-Level Cache Hieararchies", Computer Architecture, 1988 International Symposium, IEEE/IEE Publications Ondisc, pp. 73-80.

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