Data processing system having demand based write through cache w

Details Data processing system having demand based write through cache w Data processing system having demand based write through cache w

1996-10-16

1998-08-18

Eng, David Y.

395460, G06F 1208

Patent

active

057969795

ABSTRACT:
A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includes a paged cache storage having a number of lines wherein each line of the page may be, for example, 32 bytes. Each page in the cache also has several attribute bits for that page including the so called WIM and attribute bits. The W bit is for controlling write through operations; the I bit controls cache inhibit; and the M bit controls memory coherency. Since the IOCC is unaware of these page table attribute bits for the cache lines being DMAed to system memory, IOCC must maintain memory consistency and cache coherency without sacrificing performance. For DMA write data to system memory, new cache attributes called global, cachable and demand based write through are created. Individual writes within a cache line are gathered by the IOCC and only written to system memory when the I/O bus master accesses a different cache line or relinquishes the I/O bus.

REFERENCES:
patent: 3812475 (1974-05-01), Christiansen et al.
patent: 3967247 (1976-06-01), Andersen et al.
patent: 4394733 (1983-07-01), Swenson
patent: 4713755 (1987-12-01), Worley et al.

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