Excavating
Patent
1997-04-14
1999-02-02
Tu, Trinh L.
Excavating
39518506, 711113, 36424341, G11C 2900
Patent
active
058675116
ABSTRACT:
A method of determining if a requested memory block of a memory device is contained in a cache used by a processor of a computer system is disclosed. An address associated with the requested memory block is compared to a plurality of address tags stored in a cache directory of the cache, while simultaneously performing error checks on the address tags. Corrected address tags are supplied for any erroneous address tags indicated by the error checks, and any corrected address tags are also compared to the address of the requested memory block. The error check may be a parity check of a portion of the address tag, either the entire portion, or of several subsets having a number of bits smaller than the address tag. The address tags can be stored in a redundant cache directory of the cache, and the corrected address tags supplied by substituting corresponding address tags from the redundant cache directory. By moving error checking out of the critical retrieval path of the cache, the present invention results in improved performance (increased speed).
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Arimilli Ravi Kumar
Dodson John Steven
Lewis Jerry Don
Skergan Timothy M.
Dillon Andrew J.
Henkler Richard A.
International Business Machines - Corporation
Musgrove Jack V.
Tu Trinh L.
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