Method and apparatus for testing an integrated circuit including

Details Method and apparatus for testing an integrated circuit including Method and apparatus for testing an integrated circuit including

1996-08-07

1999-02-02

Nguyen, Hoa T.

Excavating

371216, G11C 2900

Patent

active

058675051

ABSTRACT:
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

REFERENCES:
patent: 3659088 (1972-04-01), Boisvert, Jr.
patent: 3664499 (1972-05-01), Sahakia
patent: 4363407 (1982-12-01), Buckler et al.
patent: 4510673 (1985-04-01), Shils et al.
patent: 5465850 (1995-11-01), Kase
patent: 5550838 (1996-08-01), Okajima

Affiliated with

Also associated with

Rating

Method and apparatus for testing an integrated circuit including does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for testing an integrated circuit including, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing an integrated circuit including will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1124285