Phase locked loop clock generator

Details Phase locked loop clock generator Phase locked loop clock generator

1993-05-14

1994-09-13

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331 74, 331DIG2, H03L 7095, H03L 710

Patent

active

053472322

ABSTRACT:
A phase locked loop (PLL) is disclosed, which produces a source clock signal which has a frequency twice that of a reference clock signal fed from the outside and is in synchronism with a reference clock signal. A timer counts pulses of a reference clock signal in order to measure time corresponding to the lock-in time of the PLL and delivers a count completion signal when the value of counting reaches a predetermined value. A start controller is in control of a clock buffer so that, after a count completion signal is delivered, the clock buffer starts feeding a source clock signal to a load circuit as an internal clock signal, in synchronism with a reference clock signal. A stop controller is also in control of the clock buffer so that, when a clock stop request signal becomes asserted, the clock buffer stops feeding an internal clock signal, in synchronism with a reference clock signal.

REFERENCES:
patent: 3795872 (1974-03-01), Napolitano et al.
patent: 4310804 (1982-01-01), Ryon
patent: 4368438 (1983-01-01), Stienstra
patent: 5008629 (1991-04-01), Ohba et al.
patent: 5126690 (1992-06-01), Bui et al.
patent: 5128632 (1992-07-01), Erhart et al.
patent: 5142247 (1992-08-01), Lada, Jr. et al.
patent: 5214677 (1993-05-01), Mori
patent: 5270669 (1993-12-01), Jokura
Young et al., "A PLL Clock Generator with 5 to 110 MHz Lock Range for Microprocessors", IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 50-51 (Feb. 1992).

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