Excavating
Patent
1996-11-18
1998-08-18
Nguyen, Hoa T.
Excavating
39518322, G06F 1100
Patent
active
057967539
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to a high speed transfer apparatus for transferring test patterns from a host computer to a pattern memory in a semiconductor test system.
BACKGROUND OF THE INVENTION
In a semiconductor test system, a large amount of test patterns to be used for semiconductor testing are read out from a disk drive of a work station and transferred to a pattern memory every time when the test items for an LSI are changed.
A conventional method, used in such a semiconductor test system, for transferring the test patterns from the disk drive of the work station to the pattern memory in a buffer memory will be described in the following with reference to FIGS. 3-5.
As shown in FIG. 3, the conventional semiconductor test system is comprised of an EWS (Engineering Work Station) 12, a tester controller 13 and a buffer memory 14. These three components are situated apart with certain distances from each other and connected by bus cables which interfere therebetween.
The EWS 12 is mainly utilized as a host computer for producing test patterns and performing debugging. The EWS 12 includes a disk drive 11 which is a large capacity storage medium to store the test patterns generated by the EWS 12.
The tester controller 13 is a control processor which manages the semiconductor test system itself.
A pattern memory 14b is a high speed memory which stores a test pattern 100 for testing an LSI which is transferred from the EWS 12. The pattern memory 14b applies the test pattern 100 to a device under test.
Reference numerals 12c, 13c, 13d and 14a are interface circuits which deal with differences in the format or speed of data between the bus cables in which data is transferred. The EWS 12 includes a temporary buffer memory 12b. The tester controller 13 includes a temporary buffer memory 13b.
The test pattern 100 is transferred from the disk drive 11 in the EWS 12 to a pattern memory 14b of the buffer memory 14 through pathways described in the following.
Namely, the test pattern 100 stored in the disk drive 11 is transferred to the memory 12b in the EWS 12 via a pathway 15 through the interface 12a.
Then, via a pathway 42, the test pattern 100 is transferred from the memory 12b to the memory 13b in the tester controller 13 through the interfaces 12c and 13c.
Next, via a pathway 43, the test pattern 100 is transferred from the memory 13b to the memory 14b in the buffer memory 14 through the interfaces 13d and 14a.
The data transfer by means of the pathway 15 includes the memory read-out from the disk drive 11 to the memory 12b through the interface 12a.
There are two ways to transfer the data by reading and writing in the memory 12b of the EWS 12 to the memory 13b of the tester controller 13 through the pathway 42 as follows: DMA (Direct Memory Access) hardware.
FIG. 4 explains the hardware structure with respect to the above data transfer (i) and (ii).
In the case of (i), a map register 13f is utilized for the data transfer which is performed by the program I/O. The map register 13f holds an offset value relative to the memory 13b of the test controller 13 viewing from a CPU 12d of the EWS 12. When accessing the memory 13b of the test controller 13 by the CPU 12d of the EWS 12, this offset value is added to an address coming from the EWS 12 side and transmitted to the address bus B; then, data of the memory 12b is transferred to the memory 13b.
In the case of (ii) for the direct memory access, a DMA address counter 12e and a DMA address counter 13e are utilized for the data transfer.
The DMA address counter 12e is used for the read-out and write-in access of the memory 12b. Before the direct memory access is taken place, the CPU 12d stores a start address of the memory 12b in the DMA address counter 12e through the data bus A and determines a number of words to be transferred. When the CPU 12d initiates the direct memory access, the DMA address counter 12e increments an address value which corresponds to the number of words per one time for the address bus A every time when one cycle of the
REFERENCES:
patent: 5243274 (1993-09-01), Kelsey et al.
patent: 5265102 (1993-11-01), Saito
patent: 5524208 (1996-06-01), Finch et al.
Advantest Corp.
Nguyen Hoa T.
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