Method of manufacturing a low voltage n-channel MOSFET device

Details Method of manufacturing a low voltage n-channel MOSFET device Method of manufacturing a low voltage n-channel MOSFET device

1978-04-17

1980-05-27

James, Andrew J.

357 41, 357 42, H01L 2978, H01L 2702

Patent

active

042053307

ABSTRACT:
A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.

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IBM Technical Disclosure Bull.; by Barson; vol. 17, No. 1 Jun. 1974, pp. 86-87.
Getting the Most Out of C-MOS Devices for Analog Switching Jobs, by Thibodeaux; Electronics, Dec. 25, 1975, pp. 69-74.

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