Boots – shoes – and leggings
Patent
1996-07-02
1998-08-18
Trammell, James P.
Boots, shoes, and leggings
711143, 711145, 711 5, 3642434, 36424341, 39520083, G06F 1208
Patent
active
057966052
ABSTRACT:
A technique for system memory space address mapping in a multiprocessor computer system is provided. The disclosed mapping architecture may be applied to a multiprocessor computer system having multiple processing nodes (SMP nodes), where each processing node may include multiple processors. The system memory address space is split into different regions such that each of the n SMP nodes is assigned 1
of the total address space. Cache coherency state information is stored for the memory in each SMP node. Memory regions may further be assigned to operate in one of three modes: normal, migratory, or replicate. When operating in normal mode, transaction to an address space assigned to a particular node are tried only locally in that node first. Transactions may be sent globally to other nodes if an improper cache coherency state is returned or if the address corresponds to a memory region assigned to another node. In migratory mode transactions are always sent globally. And in replicate mode duplicate copies of the replicate memory region are assigned to each SMP node so that transactions are always tried locally first, and only sent globally if an improper cache coherency state is returned.
REFERENCES:
patent: 4412285 (1983-10-01), Neches et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4819232 (1989-04-01), Krings
patent: 5029070 (1991-07-01), McCarthy et al.
patent: 5072369 (1991-12-01), Theus et al.
patent: 5276828 (1994-01-01), Dion
patent: 5522058 (1996-05-01), Iwasa et al.
patent: 5530933 (1996-06-01), Frink et al.
patent: 5533103 (1996-07-01), Peavy et al.
patent: 5537574 (1996-07-01), Elko et al.
patent: 5557758 (1996-09-01), Bland et al.
patent: 5579512 (1996-11-01), Goodrum et al.
patent: 5584004 (1996-12-01), Aimoto et al.
patent: 5588131 (1996-12-01), Borrill
patent: 5590335 (1996-12-01), Dubourreau et al.
patent: 5608893 (1997-03-01), Slingwine et al.
patent: 5627766 (1997-05-01), Beaven
patent: 5655103 (1997-08-01), Cheng et al.
patent: 5664147 (1997-09-01), Mayfield
patent: 5664193 (1997-09-01), Tirumalai
Cox et al., "Adaptive Cache Coherency for Detecting Migratory Shared Data," Proc. 20.sup.th Annual Symposium on Computer Architecture, May 1993, pp. 98-108.
Stenstrom et al., "An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing," Proc. 20.sup.th Annual Symposium on Computer Architecture, May 1993 IEEE, pp. 109-118.
Wolf-Dietrich Weber et al., "Analysis of Cache Invalidation Patterns in Multiprocessors", Computer Systems Laboratory, Stanford University, CA, pp. 243-256. 1989 ACM.
Kourosh et al., "Two Techniques to Enhance the Performance of Memory Consistency Models," 1991 International Conference on Parallel Processing, pp. 1-10. No date.
Li et al., "Memory Coherence in Shared Virtual Memory Systems," 1986 ACM, pp. 229-239.
D. Lenosky, PhD, "The Description and Analysis of DASH: A Scalable Directory-Based Multiprocessor," DASH Prototype System, Dec. 1991, pp. 36-56.
Hagersten et al., "Simple COMA Node Implementations," Ashley Saulsbury and Anders Landin Swedish Institute of Computer Science, 12 pages.
Saulsbury et al., "An Argument for Simple COMA," Swedish Institute of Computer Science, 10 pages.
Hagersten et al., "Simple COMA," Ashley Saulsbury and Anders Landin Swedish Institute of Computer Science, Jul. 1993, pp. 233-259.
Bui Bryan
Kivlin B. Noel
Sun Microsystems Inc.
Trammell James P.
LandOfFree
Extended symmetrical multiprocessor address mapping does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Extended symmetrical multiprocessor address mapping, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Extended symmetrical multiprocessor address mapping will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1121006