Multifunction analog-to-digital successive approximation registe

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340347M, 340347SH, 377 54, 377 64, 377 79, H03M 138

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active

046880186

ABSTRACT:
A successive approximation analog-to-digital converter, of the type which successively compares an analog level represented by binary weighted bits with an analog signal and in response thereto generates a signal indicating whether each successive binary bit should be set or reset, includes a shaft register for counting cycles during the sampling phase and generating signals for controlling the setting and resetting of each bit. Each binary bit cell includes a latch capable of assuming first and second stable states. A first string of field-effect-transistors coupled to the latch and controlled by the shift register receives a first signal indicating that the latch should be reset. A second string of field-effect-transistors coupled to the latch and controlled by the shift register receives a signal indicating that the latch should remain in a set condition.

REFERENCES:
patent: 3541446 (1970-11-01), Prozeller
patent: 3781871 (1973-12-01), Mattern
patent: 3832707 (1974-08-01), Buchanan et al.
patent: 4083043 (1978-04-01), Breuer
patent: 4592367 (1986-06-01), Imran
patent: 4598214 (1986-07-01), Sexton
Hnatek, a User's Handbook of D/A and A/D Converters, J. Wiley & Sons, Inc., 1976, pp. 268-274.
The Engineering Staff of Analog Devices, Inc., Analog-Digital Conversion Handbook, 6/1972, pp. II-46 to II-49.

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