Process for forming a trench capacitor memory cell

Details Process for forming a trench capacitor memory cell Process for forming a trench capacitor memory cell

1992-10-13

1994-09-13

Kunemund, Robert

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

053468457

ABSTRACT:
A trench capacitor memory cell having a semiconductor substrate, an active region having a transistor on a portion of the semiconductor substrate, a field region formed by removing portion of the semiconductor substrate except for portions of the active region to a certain depth below the surface of the semiconductor substrate, a capacitor trench region formed in contact with a part of the active region and within the field region, and a polysilicon plug formed within the field region except for the trench region, and insulated by being surrounded by an insulating layer.

REFERENCES:
patent: 4397075 (1983-08-01), Fatula, Jr. et al.
patent: 4830981 (1989-05-01), Baglee et al.
patent: 4921815 (1990-05-01), Miyazawa
patent: 5106774 (1992-04-01), Hieda et al.
Process Integration for 64M DRAM Using An Asymmetrical Stacked Trench Capacitor (AST) Cell by K. Sunouchi, et al. IEDM pp. 647-650 (1990).
A Surrounding Isolation-Merged Plate Electrode (SIMPLE) Cell With Checkered layout for 256MBit DRAMs and Beyond by T. Ozaki, et al. IEDM pp. 469-472 (1991).

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