Processor identification mechanism for a multiprocessor system

Details Processor identification mechanism for a multiprocessor system Processor identification mechanism for a multiprocessor system

1992-04-24

1995-02-07

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, 364240, 364241, 3642419, G06F 1300

Patent

active

053882245

ABSTRACT:
A computer system including a plurality of processors and a bus coupling the processors to one another via respective bus interfaces. The bus includes a plurality of slots for coupling the interfaces to the bus. Each interface includes an ID register coupled to the interface device, the ID register containing identification information unique to the slot of the bus used to couple the respective interface to the bus. The interface device is responsive to an address command cycle of the bus to place the identification information from the ID register on the bus during a READ bus transaction initiated by the interface and directed to another slot of the bus. A processor requiring identification of the corresponding slot causes the respective interface to initiate a READ bus transaction directed to another slot of the bus. The bus is operated so that the module at the slot to which the READ transaction is directed, returns the slot identification information to the initiator interface for communication to the corresponding processor.

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