Parallel processing system and data transfer method which reduce

Details Parallel processing system and data transfer method which reduce Parallel processing system and data transfer method which reduce

1992-03-18

1995-02-07

Bowler, Alyssa H.

Boots, shoes, and leggings

395425, 364DIG1, 3642383, 3642386, 364243, G06F 1300

Patent

active

053882202

ABSTRACT:
A parallel processing system consists of a plurality of processor elements and a network for connecting the processor elements to each other. The processor elements include a processor, a memory and a data transfer apparatus, all connected to a common bus. The data transfer apparatus includes three buffers, while a data relay includes two buffers. In data transfer from a processor element to another processor element, a data is relayed in a third processor element only with use of a buffer, or a write/read operation is not performed in the third processor element. Then, the overhead is decreased and the transfer capability is improved. Further, the data transfer apparatus does not access the common bus, so that the width of the bus can be increased, and the processing performance of the processor can be improved.

REFERENCES:
patent: 4768190 (1988-08-01), Gianearlo
patent: 5121390 (1992-06-01), Farrell et al.
patent: 5212778 (1993-05-01), Dally et al.
ICD 89-152, Integrated Circuit Symposium of the Institute of Electronics, Information, and Communication Engineers.
CPSY 89-1, Computer System Symposium of the Institute of Electronics, Information, and Communication Engineers.
W. J. Dally, et al., "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks", IEEE Transaction on Computers, vol. C-36, No. 5, 547 (1987).

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