Digital timing recovery circuit

Details Digital timing recovery circuit Digital timing recovery circuit

1993-02-09

1995-02-07

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

375 81, H03D 324

Patent

active

053881273

ABSTRACT:
An implementation efficient digital timing recovery circuit capable of being implemented without the use of multipliers. The circuit includes a voltage controlled crystal oscillator ("VCXO"), a signal generator, a non-linear operation circuit, a digital bandpass filter, a bi-quadratic filter, a digital phase lock loop circuit (DPLL) and a zero crossing detector circuit. The circuit implements a spectral line extraction technique for symbol timing recovery. A signal is received by a tuner, passed through an analog to digital converter, whose sampling rate is controlled by the timing recovery circuit, and is then supplied to a Nyquist filter. The In-phase and quadrature-phase signals output by the Nyquist filter are passed through the non-linear operation circuit to produce a signal which is then passed through the bandpass filter and then the bi-quadratic filter which has a passband centered at the symbol rate of the received signal. A quadrature output signal of the bi-quadratic filter is cross-correlated with an internal signal, generated by the signal generator as a function of the sampling rate, to produce a frequency error signal. The DPLL circuit receives the frequency error signal and uses it to generate a control signal to control the sampling rate of the A/D converter. The DPLL circuit adjusts the sampling rate until the bi-quadratic filter's output is phase locked to the output signal of the internal signal generator. A symbol decision clock signal is generated by the zero crossing detector from the signal generator.

REFERENCES:
patent: 4015083 (1977-03-01), Bellisio
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4672447 (1987-06-01), Moring et al.

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