Semiconductor integrated circuit capable of testing memory block

Details Semiconductor integrated circuit capable of testing memory block Semiconductor integrated circuit capable of testing memory block

1991-12-26

1995-02-07

Beausoliel, Jr., Robert W.

Excavating

371 223, G11C 2900

Patent

active

053881044

ABSTRACT:
A semiconductor integrated circuit includes a plurality of writable/readable memory blocks with different address spaces and an address decoder for selecting addresses of the memory blocks. The multiple memory blocks are permitted to share a part of addresses of the memory blocks in a test mode. The writing operation of one of the memory blocks that does not have the largest address space is disabled during a period in which address signals for commonly performing an address scan of individual memory blocks exceeds the address width of that memory block. It is therefore possible to permit a plurality of memory blocks with different address spaces mounted on the same chip to be tested with high precision and without additional burden on the generation of test vectors or on a BIST (built-in self test) test circuit.

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L. Basto et al, "Testing the MC68030 Caches," Sep. 1-3, 1987, International Test Conference 1987 Proceedings, pp. 826-833.
W. Finsterbusch, "Speicherschaltkreis mit selbsttestenden Eigenschaften," Nachrichten Technik Elektronik, vol. 36, No. 9, 1986, pp. 333-335.

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