Process for manufacture of MOS gated device with reduced mask co

Details Process for manufacture of MOS gated device with reduced mask co Process for manufacture of MOS gated device with reduced mask co

1994-09-01

1998-08-18

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 40DM, H01L 21265

Patent

active

057957932

ABSTRACT:
A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask to sequentially form a cell body and a source region within the cell body, and a second mask step to form, by a silicon etch, a central opening in the silicon surface at each cell and to subsequently undercut the oxide surrounding the central opening. A contact layer then fills the openings of each cell to connect together the body and source regions. Only one critical mask alignment step is used in the process.

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