Patent
1994-04-28
1997-08-19
Lim, Krisna
395580, 395582, G06F 938
Patent
active
056597223
ABSTRACT:
A data processing system includes a number of processing elements wherein each of the processing elements generates one or more condition signals, one or more memory elements associated with the processing elements for storing instructions and data associated with the processing elements, at least one register for storing a predicate associated with each of the processing elements and logic for comparing condition signals from each of the processing elements with a corresponding predicate to generate one or more branch test signals, and combination logic to provide a single take branch signal based on branch test signals and logic masks associated with each of the predicates.
REFERENCES:
patent: 3764988 (1973-10-01), Onishi
patent: 4439828 (1984-03-01), Martin
patent: 4742451 (1988-05-01), Bruckert et al.
patent: 4766566 (1988-08-01), Chuang
patent: 4827402 (1989-05-01), Wada
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4853840 (1989-08-01), Shibuya
patent: 4903196 (1990-02-01), Pomerene et al.
patent: 4974155 (1990-11-01), Dolong et al.
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5075844 (1991-12-01), Jardine et al.
patent: 5081574 (1992-01-01), Larsen et al.
patent: 5093908 (1992-03-01), Beacom et al.
patent: 5101344 (1992-03-01), Bonet et al.
patent: 5142634 (1992-08-01), Fite et al.
patent: 5185868 (1993-02-01), Tran
patent: 5197135 (1993-03-01), Eickemeyer et al.
patent: 5197136 (1993-03-01), Kimura et al.
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5283873 (1994-02-01), Steely, Jr. et al.
patent: 5347639 (1994-09-01), Rechtschaffen et al.
patent: 5349671 (1994-09-01), Maeda et al.
patent: 5418917 (1995-05-01), Hiraoka et al.
patent: 5421026 (1995-05-01), Sato
Microprocessors and Microsystems, vol. 14, No. 6, Jul. 1990 --Aug. 1990, London, GB, pp. 357-366, XP00 151093 "RISC System/6000 Processor Architecture", Groves & Oehler.
Microprocessing and Microprogramming, vol. 36, No. 5, Oct. 1993, Amsterdam, NL, pp. 259-278, XP000397908 "ALU Design and Processor Branch Architecture", GB Steven & FL Steven.
Computer Architecture News, vol. 18, No. 4, Dec. 1990, New York, US, pp. 35-51, XP000201913, Yen-Jen Oyang et al.: "Effect of Employing Advanced Branching Mechanisms in Superscaler Processors".
IBM Technical Disclosure Bulletin, V. 25, No. 1, Jun. 1982, pp. 136-137 "New Condition Code and Branch Architecture for High Performance Processors".
ESA/390 Principles of Operation, IBM Publication No. SA22-7201-00 (1992).
Assembler Language Reference for AIX Version 0.3 for RISC System/6000, IBM Publication No. SC23-2197 (1992).
Emma, et al., "Multiple Queued Condition Codes," IBM Technical Disclosure Bulletin, vol. 31, No. 2, Jul. 1988, pp. 294-296.
Colwell, et al., "A VLIW Architecture for a Trace Scheduling Compiler," IEEE Transactions on Computers, vol. 37, No. 8, Aug. 1988, pp. 967-979.
Ebcioglu and Kumar, "A Wide Instruction Word Architecture for Parallel Execution of Logic Programs Coded in BSL," New Generation Computing, vol. 7, (1990), pp. 219-242.
Acosta, R. D., et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions on Computers, Fall, C-35 No. 9, Sep. 1986, pp. 815-828.
Anderson, V. W., et al., The IBM System/360 Model 911, "Machine Philosophy and Instruction Handling," Computer Structures: Principles and Examples, Siewiorek, et al., ed., McGraw-Hill, 1982, pp. 276-292.
Capozzi, A. J., et al., "Non-Sequential High-Performance Processing," IBM Technical Disclosure Bulletin vol. 27, No. 3, Oct. 1984, pp. 2842-2844.
Chan, S. et al., "Building Parallelism into the Instruction Pipeline," High Performance Systems, Dec. 1989, pp. 53-60.
Murakami, K. et al., "SIMP (Single Instruction Stream/Multiple Instruction Pipelining)"; A Novel High-Speed Single Processor Architecture, Proceedings of the Sixteenth Annual Symposium on Computer Architecture, 1989, pp. 78-85.
Smith, J. E., "Dynamic Instructions Scheduling and the Astronautics ZS-1," IEEE Computer, Jul. 1989, pp. 21-35.
Smith, M. D., et al., "Limits on Multiple Instruction Issue," ASPLOS III, 1989, pp. 290-302.
Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," Computer Structures, Principles, and Examples (Siewiorak, et al., ed.), McGraw-Hill, 1982, pp. 293-302.
Wulf, P. S., "The WM Computer Architecture," Computer Architecture News, vol. 16, No. 1, Mar. 1988, pp. 70-84.
Jouppi, N. P., et al., "Available Instruction-Level Parallelism for Superscaler Pipelined Machines," ASFLOS III, 1989, pp. 272-282.
Jouppi, N. P. "The Non-Uniform Distribution of Instruction-Level and Machine Parallelism and its Effect on Performance," IEEE Transactions on Computers, vol. 38, No. 12, Dec. 1989, pp. 1645-1658.
Ryan, D. E., "Intel's 80960: An Architecture Optimized for Embedded Control," IEEE Microcomputers, vol. 8, No. 3, Jun. 1988, pp. 63-76.
Eberhard, R. J., IBM Technical Disclosure Bulletin, vol. 33, No. 10A, Mar. 1991.
Berenbaum, A. D., "Introduction to the CRISP Instruction Set Architecture," Proceedings of COMPCON, Spring 1987, pp. 86-89.
Bandyopadhyay, S., et al., "Compiling for the CRISP Microprocessor," Proceedings of COMPCON, Spring 1987, pp. 96-100.
Hennessy, J., et al., "MIPS: A VSI Processor Architecture," Proceedings of the CMU Conference on VLSI Systems and Computations, 1981, pp. 337-346.
Patterson, E. A., "Reduced Instruction Set Computers," Communications of the ACM, vol. 28, No. 1, Jan. 1985, pp. 8-21.
Radin, G., "The 801 Mini-Computer," IBM Journal of Research and Development, vol. 27, No. 3, May 1983, pp. 237-246.
Ditzel, D. R., et al., "Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero," Proceedings of COMPCON, Spring 1987, pp. 2-9.
Hwu, W. W., et al., "Checkpoint Repair for High-Performance Out-of-Order Execution Machines,"IEEE Transactions on Computers, vol. C36, No. 12, Dec. 1987, pp. 1496-1594.
Lee, J. K. F., et al., "Branch Prediction Strategies in Branch Target Buffer Design," IEEE Computer, vol. 17, No. 1, Jan. 1984, pp. 6-22.
Riseman, E. M., "The Inhibition of Potential Parallelism by Conditional Jumps," IEEE Transactions on Computers, Dec. 1972, pp. 1405-1411.
Smith, J. K. "A Study of Branch Prediction Strategies," IEEE Proceedings of the Eighth Annual Symposium on Computer Architecture, May 1981, pp. 135-148.
Archibold, James, et al., Cache Coherence Protocols: "Evaluation Using a Multiprocessor Simulation Model," ACM Transactions on Computer Systems, vol. 4, No. 4, Nov. 1986, pp. 273-398.
Baer, J. L., et al., "Multi-Level Cache Hierarchies: Organizations, Protocols, and Performance," Journal of Parallel and Distributed Computing, vol. 6, 1989, pp. 451-476.
Smith, A. J., "Cache Memories," Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 473-530.
Smith, J. K., et al., "A Study of Instruction Cache Organizations and Replacement Policies," IEEE Proceedings of the Tenth Annual International Symposium on Computer Architecture, Jun. 1983, pp. 132-137.
Vassiliadis, S., et al., "Condition Code Predictory for Fixed-Arithmetic Units," International Journal of Electronics, vol. 66, No. 6, 1989, pp. 887-890.
Tucker, S. G., "The IBM 3090 System: An Overview," IBM Systems Journal, vol. 25, No. 1, 1986, pp. 4-19.
IBM Publication No. SA22-7200-0, Principles of Operation, IBM Enterprise Systems Architecture/370, 1988.
Kogge, Peter M., The Architecture of Pipelined Computers, Hemisphere Publishing Corp., 1981.
Blaner Bartholomew
Larsen Larry D.
Clark George E.
International Business Machines - Corporation
Lim Krisna
Phillips Steven B.
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