Data processor including memory for associating data elements of

Details Data processor including memory for associating data elements of Data processor including memory for associating data elements of

1995-07-05

1997-08-19

Kulik, Paul V.

395456, 395474, 395480, 39549704, 395412, 395612, 395621, G06F 1730, G06F 1208

Patent

active

056597142

ABSTRACT:
There is disclosed a data processor in which the execution of a program, typically classical relaxation, for accessing a large number of data elements on edges of a multi-dimensional array requires a smaller number of buffer lines or cache lines and a smaller number of packets for a buffer memory or cache memory to transmit packets for holding and controlling groups of a plurality of data elements at sequential addresses in a memory, accomplishing efficient data processing. A shared-memory multiprocessor system which is an example of the data processor comprises nodes (N) each including a memory (45) for associating data elements of two-dimensional array which are numbered in spiral order with element numbers thereof to store the data elements at sequential addresses, a cache memory (43) for accessing a main memory of another node by means of packet transmission, and computing elements (41, 42).

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The 17th Annual Symposium on Computer Architecture, Jun. 1990, pp. 1-13, Anant Agarwal, et al., "Apr.: A Processor Architecture for Multiprocessing".
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Tien-Pao Shih et al., "Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs," 1994 Int'l Conf. on Parallel and Distributed Systems, IEEE, pp. 558-566.
Chi-Hung Chi et al., "Reducing Memory Latency Using a Small Software Driven Array Cache," 1995 Annual Hawaii Int'l Conf. on System Sciences, vol. I, IEEE, pp. 202-210.

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