Write-back and snoop write-back buffer to prevent deadlock and t

Details Write-back and snoop write-back buffer to prevent deadlock and t Write-back and snoop write-back buffer to prevent deadlock and t

1994-10-03

1997-08-19

Chan, Eddie P.

395468, G06F 1208

Patent

active

056597096

ABSTRACT:
A multiprocessor computer system includes specially designed snoop circuitry to prevent data loss during write-back cycles. A memory controller within a main memory module determines if a data request at a specified address corresponds to a cacheable memory address. If it is determined that the requested data is located at a cacheable memory address, then the memory controller initiates a snoop cycle. When a snoop cycle is initiated, a write-back buffer within the main memory module is first examined to determine if data contained within the write-back buffer is the requested data, so that the data within the write-back buffer has an associated address which is the designated cacheable memory address. If the write-back buffer does not contain the requested data, then the memory controller causes the cache memories associated with the multiple processors within the multiprocessor system to be examined. If any of these cache memories contain data at the specified cacheable address, and the data at this address has been modified by the local processor without being written back to the main memory module, then the data at the specified address is immediately written back to the main memory module. In order to prevent overwriting of data contained within the write-back buffer, the multiprocessor system includes a snoop write-back buffer which serves as a bypass buffer to bypass the write-back buffer without overwriting the data contained within the write-back buffer.

REFERENCES:
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patent: 5479636 (1995-12-01), Vanka et al.
Memory Controller/PCI Host Bridge Engineering Hardware Specification; Revision: R2-0.1; Published May 27, 1994; Document No. IBM27-82P54; IBM Microelectronics.

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