Method of forming an array of non-volatile sonos memory cells an

Details Method of forming an array of non-volatile sonos memory cells an Method of forming an array of non-volatile sonos memory cells an

1994-05-05

1995-02-07

Thomas, Tom

Fishing, trapping, and vermin destroying

437 44, 437 48, H01L 2170

Patent

active

053875346

ABSTRACT:
An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; c) a word line commonly interconnecting the adjacent SONOS gates of the pair; and d) separate bit lines separately electrically engaging the separated diffusion regions of the pair. LDD regions are also included. A method of producing such a construction is disclosed.

REFERENCES:
patent: 4914050 (1990-04-01), Shibata
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patent: 5234856 (1993-08-01), Gomzalez
patent: 5278438 (1994-01-01), Kim et al.
Kazerounian, R. et al.; Alternate Metal Virtual Ground Eprom Array Implemented in a 0.8um Process for Very High Density Applications, IEDM 91-311, pp. 11.5.1-11.5.4 (1991).
Nozaki et al.; A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application, IEEE Jnl. of Solid State Circuits, vol. 26, No. 4, pp. 497-501, (Apr. 1991).
Chang, Joseph; Nonvolatile Semiconductor Memory Devices, IEEE, vol. 64, No. 7, pp. 1039-1059, (Jul. 1976).

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