System with reduced instruction set processor accessing plural m

Details System with reduced instruction set processor accessing plural m System with reduced instruction set processor accessing plural m

1991-09-27

1995-01-31

Coleman, Eric

Boots, shoes, and leggings

3642403, 3642395, 36423223, 364254, 364DIG1, 395800, G06F 1300

Patent

active

053865375

ABSTRACT:
A data processor adopts a CPU that is represented by an RISC type CPU and capable of processing one instruction in one clock cycle. The data processor has an instruction bus and a data bus independently of each other and includes an EPROM connected to the instruction bus and a DRAM connected to the data bus. The RISC type CPU accesses the EPROM with no wait states and the DRAM with one wait state.

REFERENCES:
patent: 4953082 (1990-08-01), Nomura
patent: 5097437 (1992-03-01), Larson
patent: 5247644 (1993-09-01), Johnson
patent: 5287470 (1994-02-01), Simpson
Am29000 Memory Design Handbook, Mark McLain, and Sherman Lee; 1989 Advanced Micro Devices.
Introducing the Intel i860 64-Bit Microprocessor, IEEE, 1989 Aug., pp. 15-30.

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