Programmable memory array control signals

Details Programmable memory array control signals Programmable memory array control signals

1987-06-18

1988-11-15

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365189, G11C 1300

Patent

active

047854286

ABSTRACT:
The waveform of a strobe type signal (70) is specified by two bit strings (72, 74) stored in the RAM (20), one bit string (72) denoting when the strobe is to be reset and the other (74) denoting when the strobe is to be set. The bit positions in the bit strings correspond with clock cycles (76) taken for a DRAM memory access. The bit positions are written by means of addressable registers (71) corresponding to rows (e.g. 80-87) of the RAM. A one bit in the set bit string (72) causes the signal (70) to be asserted in the corresponding clock cycle of the request. A one bit in the reset bit string causes the signal (70) to be de-asserted in the corresponding clock cycle of the request. The set and reset times are fine-tuned to a fraction of a cycle by providing a multi-bit fractional cycle index field (78) to accompany each bit string. If a two bit quarter cycle index (QCI) field is used, the boundaries of the quarter cycles are numbered from 0 to 3. 0 coincides with the first quarter cycle after the leading edge of a clock cycle and 3 coincides with the clock cycle boundary. The one bit in the set or reset bit string denotes the cycle in which a transition is to take place, while the quarter cycle index field encoding denotes the precise quarter of the cycle in which the transition takes place.

REFERENCES:
patent: 4494223 (1985-01-01), Reddy et al.

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