Boots – shoes – and leggings
Patent
1985-08-20
1988-11-15
Chan, Eddie P.
Boots, shoes, and leggings
G06F 1300
Patent
active
047854146
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention relates to computer systems and the general object of the invention is to increase the capacity and software security of binary computers by means of logic circuitry, which is interposed between a standard CPU, (such as one represented by Motorola MC68000, INTEL 80286 etc.) and the memory accessed from this CPU.
SUMMARY OF THE INVENTION
The invention provides a computer system having a central processing unit and a main memory for storage of information in binary form and a master control unit for performing individual and selected range checking and range conversion by reading of information from an internal memory of the master control unit, the internal memory of the master control unit containing a Data Descriptor Table for each individually accessible data element with two elements of each description table entry assigned for range check and conversion purposes, one of which elements permits one of the extreme limits of the value range of the data element associated with the Data Descriptor Table entry to be determined and the second of which allows the number of values in the value range of the associated data elements to be determined, and also includes a set of arithmetic circuits interposed in the data path to and from the main memory to be utilised for each read or write of information to and from the main memory, whereby the arithmetic circuits receive their input from the main memory and from the Data Descriptor Table entry associated with a data element in the main memory and deliver their output to the central processor unit by reading of information from the main memory and also receive input from the central processor unit and the Data Descriptor Table entry associated with a data element in the main memory and deliver a corresponding output to the main memory, the master control unit having means for generating an interrupt signal to the central processor unit in the case of an out of range value being detected.
The invention thus allows range checks, and conversions which otherwise would have to be explicitly coded into a programme to be performed automatically, thereby reducing the code volumes and permitting faster execution. The invention also raises the software security within the computer because there is no way that the programmer can forget to perform, or deliberately omit, the range checks and conversions in order to speed up the execution of a programme.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a block diagram of a conventional binary computer.
FIG. 2 is a chart showing a typical set of binary numbers, together with three alternative decimal schemes corresponding to the binary numbering.
FIG. 3 is partially a block diagram illustrating a typical algebraic operation performed by an arithmetic logic unit in the computer of FIG. 1.
FIG. 4 is a block diagram showing a computer system with a master control unit, in accordance with the present invention.
DETAILED DESCRIPTION
Computers conventionally operate in binary mode, i.e. information is stored and treated in binary form. This is illustrated by FIGS. 1, 2 and 3. FIG. 1 shows a typical binary computer consisting of a Central Processing Unit (CPU) and a Main Memory (M). The CPU is connected to M via an Address Bus (ABUS) with k address bits, a Data Bus (DBUS) with 16 data bits and two control connections (R and W).
The number of data bits on the data bus corresponds with the Word Length of the Main Memory (M), i.e. the number of data bits in each memory word, which in this example is assumed to be 16 bits. Each memory word can therefore assume 2.sup.16 =65536 different values.
The number of address bits on the Address Bus (K) defines the number of addressable memory words which is 2.sup.k. The address of each of these words is defined by the corresponding values 0.1 . . . 2.sup.k-1.
The CPU consists of a number of elements of which the most important for the purpose of this description are the Micro Program Unit (MPU), the Arithmetic-Logic Unit (ALU), the Address Register (AR), th
REFERENCES:
patent: 3930232 (1975-12-01), Wallach et al.
patent: 3945002 (1976-03-01), Duttweiler et al.
patent: 4542456 (1985-09-01), Hill
Computer Architecture News, vol. 9, No. 4, Jun. 15, 1981, N.Y. (U.S.), D. D. Hill: "A Hardware Mechanism for Supporting Range Checks", pp. 15-21, see p. 18, paragraph 1; p. 19, paragraph 3; p. 20, paragraphs 1, 2.
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