Multiprocessor coherent cache system including two level shared

Details Multiprocessor coherent cache system including two level shared Multiprocessor coherent cache system including two level shared

1986-06-27

1988-11-15

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

047853956

ABSTRACT:
A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units. For completely independent operation, each processing unit is allocated one-half of the total available cache memory space by separate accounting replacement apparatus included within the buffer memory stage. A multiple allocation memory (MAM) is also included in the buffer memory stage. During each directory allocation cycle performed for a processing unit, the allocated space of the other processing unit is checked for the presence of a multiple allocation. The address of the multiple allocated location associated with the processing unit having the lower priority is stored in the MAM allowing for earliest data replacement thereby maintaining data coherency between both independently operated processing units.

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