Rectangular array signed digit multiplier

Details Rectangular array signed digit multiplier Rectangular array signed digit multiplier

1991-12-24

1993-02-02

Mai, Tan V.

Boots, shoes, and leggings

3647462, G06F 752

Patent

active

051843188

ABSTRACT:
A rectangular array signed digit multiplier circuit 10 is disclosed which comprises a multiplier core (28). The circuit (10) comprises a C-latch (14), a D-latch (18), and A-latch (26), and a feedback latch (52) operable to store operands to be input into the multiplier core (28) through a MULTIPLIER INPUT, a multiplicand INPUT, an ADDER INPUT and a FEEDBACK INPUT, respectively. The product output by the multiplier core (28) may comprise the sum of the product of the values input through the MULTIPLIER INPUT and MULTIPLICAND INPUT and the ADDER and FEEDBACK INPUTS. The product is stored in a result latch (40) and may be used in subsequent passes through multiplier core (28) through the use of a data path coupling result latch (40) with feedback latch (52). Multiplier core (28) comprises a series connection of a times three adder level (56), a Booth recoder level (58), a partial product generator level (60), a level one adder level (62), a level two adder level (64) and a level three adder level (66).

REFERENCES:
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4594678 (1986-06-01), Uhlenhoff
patent: 4760544 (1988-07-01), Lamb
patent: 4878190 (1989-10-01), Darley et al.
patent: 5047973 (1991-09-01), Steiss et al.

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