Semiconductor memory device, operating synchronously with a cloc

Details Semiconductor memory device, operating synchronously with a cloc Semiconductor memory device, operating synchronously with a cloc

1993-05-28

1995-01-31

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

3652335, G11C 11408

Patent

active

053863917

ABSTRACT:
The semiconductor memory device is improved so as to be simplified and to cope with a high speed CPU by allowing the CPU and the memory device to be controllable by only a single clock. The address control sections are operated on the basis of a monoperiod clock signal CLK and a group of control signals. The column address is applied to a plurality of divided memory cell arrays, respectively, so that the memory cell arrays can be interleaved with each other. The input and output buffers controlled by the input and output control section 1 are operated in pipeline processing, to increase the access speed of data read from or written in the memory cell arrays 17 and 18.

REFERENCES:
patent: 5155705 (1992-10-01), Goto et al.
patent: 5274596 (1993-12-01), Watanabe

Affiliated with

Also associated with

Rating

Semiconductor memory device, operating synchronously with a cloc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, operating synchronously with a cloc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device, operating synchronously with a cloc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1106497