Semiconductor memory with looped shift registers as row and colu

Details Semiconductor memory with looped shift registers as row and colu Semiconductor memory with looped shift registers as row and colu

1993-04-08

1995-01-31

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365221, 36523008, 377 73, G11C 1300

Patent

active

053863909

ABSTRACT:
Address pointers (11, 12, 13, 14) include flip-flop circuits and flip-flop circuits including data through circuits. A control circuit (10) controls the flip-flop circuits such that the data through circuits of unnecessary flip-flop circuits cause data to pass through to prevent the flip-flop circuits from selecting unnecessary memory cells (7). The control circuit (10) generates control signals in selection signal producing means including fuses and the like and a decoding portion. Since the decoding portion decodes a flip-flop selection signal, the number of fuses is reduced. This achieves a semiconductor memory comprising address parts for memory cell selection and redundancy circuits which has a reduced area for provision of the fuses for providing redundancy to the semiconductor memory.

REFERENCES:
patent: 4903242 (1990-02-01), Hamaguchi et al.
patent: 5198999 (1993-03-01), Abe et al.
patent: 5327386 (1994-07-01), Fudeyasu

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