MOS register for selecting among various data inputs

Details MOS register for selecting among various data inputs MOS register for selecting among various data inputs

1984-09-04

1987-02-24

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307279, H03K 17693

Patent

active

046459448

ABSTRACT:
In a high speed latching circuit (C) for selectively receiving one or plural slowly changing input data signals and latching them at high speed, one or plural first CMOS FETs (31, 33, 35, 37) and one or plural second CMOS FETs (32, 34, 36, 38) of p-conductivity type are connected in series respectively to form one or plural series connections (31+32, 33+34, 35+36, 37+38), wherein selection signals are given to the gates of the first CMOS FETs, input data signals are given to the gates of the second CMOS FETs and a flip-flop (30+39+41) is driven by selected one of the series connections.

REFERENCES:
patent: 4390987 (1983-06-01), Best
patent: 4447892 (1984-05-01), Zibu
patent: 4463273 (1984-07-01), Dingwall
patent: 4558237 (1985-12-01), Rabe et al.
patent: 4559608 (1985-12-01), Young et al.
patent: 4563594 (1986-01-01), Koyama
Pomerantz, "Complementary MOS J-K Flip-Flop and Shift Cell", IBM T.D.B., vol. 16, No. 11, Apr. 1974, pp. 3613-3614.

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