Boots – shoes – and leggings
Patent
1991-10-17
1994-11-15
Black, Thomas G.
Boots, shoes, and leggings
364488, G06F 1560
Patent
active
053654544
ABSTRACT:
In a layout designing method for an LSI by a CMOS standard cell method, layout cells (standard layout patterns) which respectively correspond to logical function units are selected from a library. In this selection, the respective layout cells are selected from the library as patterns which are divided into p-type layout cells and n-type layout cells. The p-type layout cells and the n-type layout cells are arranged in accordance with a predetermined logical circuit diagram. Interconnection patterns for interconnecting the p-type layout cells and for interconnecting the n-type layout cells are arranged in accordance with the logical circuit diagram. An excessive interconnection region can be minimized, and efficient interconnections can be achieved. Therefore, an occupied plane area can be reduced in the layout design.
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Weste et al., "CMOS Standard Cell Design", Principles of CMOS VLSI Design-A Systems Perspective, pp. 193-195, 1985.
Kawai Hiroyuki
Nakagawa Shin-ichi
Black Thomas G.
Mitsubishi Denki & Kabushiki Kaisha
Wieland Susan
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