Method for manufacturing vertical MOS transistors

Details Method for manufacturing vertical MOS transistors Method for manufacturing vertical MOS transistors

1993-12-09

1995-01-31

Fourson, George

Fishing, trapping, and vermin destroying

437203, 437 67, 437913, 257490, 148DIG126, H01L 21265

Patent

active

053858522

ABSTRACT:
For manufacturing vertical MOS transistors, doped regions for a drain (11), well (3), and source (4) are formed in a vertical sequence in a substrate (1). Using a Si.sub.3 N.sub.4 mask (5), trenches (6) are etched perpendicular to the surface of the substrate (1). The trenches isolate the source (4) and well (3) structure, and are filled with doped polysilicon and are closed in an upper region with an insulation structure (8) in self-aligned fashion on the basis of local oxidation. The insulation structure (8) projects laterally beyond the trenches (6). Using the insulation structure (8) as an etching mask, via contact holes (9), that are provided with a metallization for contacting the source (4) and the well (3), are opened down into the well (3) between neighboring trenches (6).

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Article entitled "An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process" by D. Ueda et al., IEEE vol. ED-34, Apr. 1987 pp. 926-930.
Article entitled "A 55-V, 0.2 m.OMEGA.. cm.sup.2- Vertical Trench Power MOSFET" by K. Shenai, IEEE Ed Lett. vol. 12, Mar. 1991, pp. 108-110.
Article entitled "500-V n-Channel Insulated-Gate Bipolar Transistor with a Trench Gate Structure", by, H.-R. Chang et al., IEEE Transactions on Electron Devices, vol. 36, No. 9, Sep. 1989, pp. 1824-1829.

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