Method of making low resistance polysilicon gate transistors and

Details Method of making low resistance polysilicon gate transistors and Method of making low resistance polysilicon gate transistors and

1983-06-15

1984-10-30

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29591, 148175, 148187, 357 59, H01L 21263, H01L 754

Patent

active

044798318

ABSTRACT:
In the disclosed method, a transistor is fabricated by depositing an unpatterned layer of silicon on an insulating layer over a surface of a semiconductor substrate, with the silicon layer being deposited in an amorphous state to improve its uniformity in thickness and smoothness. Subsequently, while the silicon layer is still in the amorphous state, it is patterned by removing selected portions to form a gate. This patterning in the amorphous state improves the gates edge definition. Thereafter, the patterned amorphous silicon layer is heated to change it to polycrystalline silicon, thereby increasing its stability and conductivity.

REFERENCES:
Chou, IBM-TDB., 14 (1971) 250.

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