Input protection MOS semiconductor device with zener breakdown m

Details Input protection MOS semiconductor device with zener breakdown m Input protection MOS semiconductor device with zener breakdown m

1985-06-26

1986-09-02

James, Andrew J.

357 2314, 357 41, 357 42, 357 13, 357 237, H01L 2994, H01L 2990

Patent

active

046099310

ABSTRACT:
A p.sup.- -type well region is formed in a n.sup.- -type semiconductive substrate. An n-channel metal oxide semiconductor field effect transistor (N-MOSFET) is formed in the p.sup.- -type well region. The p.sup.- -type well region is electrically insulated from an external potential such as the ground potential. The gate electrode of the N-MOSFET is connected to the p.sup.- -type well region. When the N-MOSFET is used as an input protective device of a CMOS integrated circuit, an n.sup.+ -type layer corresponding to the source electrode of the N-MOSFET is grounded, while another n.sup.+ -type layer corresponding to the drain electrode thereof is connected to an input terminal of the CMOS integrated circuit through a resistor.

REFERENCES:
patent: 3469155 (1969-09-01), VanBeek
patent: 3470390 (1969-09-01), Lin
patent: 3512058 (1970-05-01), Khajezadeh et al.
patent: 3739238 (1973-06-01), Hara
patent: 3806773 (1974-04-01), Watanabe
patent: 4282556 (1981-08-01), Ipri

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