Fishing – trapping – and vermin destroying
Patent
1993-10-12
1994-11-15
Thomas, Tom
Fishing, trapping, and vermin destroying
437909, H01L 21265
Patent
active
053648072
ABSTRACT:
A method for fabricating an asymmetry HS-GOLD MOSFET by use of a photo etch process in place of a large tilt implantation process, capable of improving a packing density and reducing a junction capacitance of a source region, thereby improving a characteristic of a device to be finally produced. The method includes the steps of forming a gate insulating film and a gate on a p.sup.- type semiconductor substrate, implanting n type impurity ions in the semiconductor substrate so as to symmetrically form n.sup.- type source and drain regions in the semiconductor substrate, forming an insulating film over the entire exposed surface of the resulting structure, subjecting the insulating to an anisotropic etching to form spacers at respective side walls of the gate, implanting n type impurity ions in the semiconductor substrate so as to form n.sup.+ type high concentration source and drain regions respectively adjacent to the n.sup.- type source and drain regions, coating a photoresist film over the entire exposed surface of the resulting structure, subjecting the photoresist film to a patterning to expose one of the spacers disposed toward the source region, removing the exposed spacer, and implanting p type impurity ions in the semiconductor substrate through an area defined by removal of the spacer so as to form a p type halo region.
REFERENCES:
patent: H000986 (1991-11-01), Codella et al.
patent: 5043294 (1991-08-01), Willer et al.
patent: 5063172 (1991-11-01), Manley
patent: 5296398 (1994-03-01), Noda
Wolf et al., vol. II, Silicon Processing for the VLSI Era, Lattice Press, 1990, section 5.6.7, pp. 362-363.
Goldstar Electron Co. Ltd.
Gurley Lynne A.
Thomas Tom
LandOfFree
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