CCD charge substraction arrangement

Details CCD charge substraction arrangement CCD charge substraction arrangement

1982-05-28

1985-04-02

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Charge transfer device

Charge-coupled device

377 60, 377 61, 357 24, 358 31, 333165, G11C 1928, H03H 730

Patent

active

045091811

ABSTRACT:
Charge subtraction for charge packets of two charge transfer device (CTD) delay lines is provided by alternately transferring them under a periodically clamped, normally floating sense gate, common to both delay lines. Adjacent the sense electrode, each delay line includes preceding and succeeding transfer gates, the gates of each line clocked by one of first and second oppositely phased clock signals for alternately transferring the charge packets under the sense gate. A reset switch clamps the sense gate to a reference voltage whenever its input voltage exceeds a first threshold level and unclamps the gate whenever its input voltage falls below the first threshold level.
The clock signal applied to the gates of one of the delay lines is also applied to the input of the reset switch and includes an amplitude excursion which sequentially falls below the first threshold level which unclamps the sense gate and then falls below a second threshold level which causes a charge packet from the preceding gate of that one line to transfer in under the sense gate. Since a single amplitude transition of one of the clock signals includes both the threshold levels for performing these functions, the time delay between these functions is minimized. The second, oppositely phased clock signal, is applied to the other of the two delay lines and includes an amplitude excursion which increases above a third threshold level for causing a charge packet to transfer out from under the sense gate into the succeeding gate at a time after the first clock signal has fallen below the second threshold level. This results in a minimum amount of time for causing charge packet transfer under the sense gate while it is unclamped and provides a maximum amount of time for accurately sampling the subtractive combination of the charge packets sensed by the sense gate.

REFERENCES:
patent: 4090095 (1978-05-01), Herrmann
patent: 4096516 (1978-06-01), Pritchard
patent: 4123733 (1978-10-01), Poirer
patent: 4139784 (1979-02-01), Sauer
patent: 4255725 (1981-03-01), Berger et al.
patent: 4337403 (1982-06-01), Berger et al.

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