Sampling waveform digitizer for dynamic testing of high speed da

Details Sampling waveform digitizer for dynamic testing of high speed da Sampling waveform digitizer for dynamic testing of high speed da

1983-10-20

1987-02-03

Wise, Edward J.

Boots, shoes, and leggings

324 77A, 324121R, G01R 2316, G06F 1531

Patent

active

046412468

ABSTRACT:
A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The system includes latching comparators which are supplied with the waveform under test and the comparator digital output is integrated by an operational amplifier integrator and fed back to the reference input of the latching comparator to form a comparator-integrator loop. A circuit provides strobe pulses which repeatedly sample the latch enable input of the comparators at a selected time/point until the integrator feedback forces the comparator reference input to be equal to the sample value of the input signal. At this point, an equilibrium state is reached where the integrator output oscillates about the sampled value, and when the loop settles, an analog-to-digital converter reads the final value under computer command. The sample point is computer controlled through a programmable delay line. A modified T-filter system operatively coupled between the output of the latching comparator and the input of the operational amplifier allows control of the integrator slope and filters out signal spikes to allow the required accuracy for high speed measurements while a similar modified T-filter is provided in the feedback loop for preventing disturbances at the integrator output which could be caused by the sampling of the latching comparators and for simultaneously preventing ringing and for rounding off signal spikes in the feedback loop. Various adaptions of the broad sampling digitizer system are provided for measuring the settling time of a 12-bit digital-to-analog converter whose common mode output reading is one-half LSB accuracy in under 40 nanoseconds and a dynamic tester for very fast-acting sample and hold amplifier circuits which measure, by independently controlling the polarity of the square wave or test stimulus signal and the polarity of the hold select command, such circuit parameters as acquisition time, sample-to-hold settling time, sample-to-hold offset, glitch amplitude, amplitude delay, hold mode feedthrough rejection, risetime, slew rate, and the like.

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