Sense amplification scheme for random access memory

Details Sense amplification scheme for random access memory Sense amplification scheme for random access memory

Filed on

1981-10-09

Date issued

1983-12-20

Examiner

Anagnos, Larry N.

Patent Class

Electrical transmission or interconnection systems

SubClass

Nonlinear reactor systems

SubSubClass

Parametrons

Other Related Categories

307594, 307596, 365205, H03K 524, G01R 19165, G11C 706

Type

Patent

Status

active

Patent number

044219962

Description

ABSTRACT:
In source-clocked type of cross-coupled latch sense amplifier of a dynamic random access memory device, there is provided a sense clock that employs multiple extended dummy memory cells to provide reference timing which tracks time constants of word line, cell transfer gate, cell capacitor, and bit line, and the sense clock is further compensated over large variations of fabrication process parameters and operating conditions. The trigger and slave clock circuit are chained in series to control the timing sequence of a plurality of clocked output signals. The clocked output signals are selectively amplified and summed in parallel to generate current with an intended dynamic characteristic. The current so generated is applied to the common source electrodes of the cross-coupled latch.

REFERENCES:
patent: 4021682 (1977-05-01), Elmer et al.
patent: 4050061 (1977-09-01), Kitagawa
patent: 4119870 (1978-10-01), Zibert
patent: 4119871 (1978-10-01), Zibert
patent: 4158241 (1979-06-01), Takemae
patent: 4195239 (1980-03-01), Suzuki
patent: 4239993 (1980-12-01), McAlexander et al.
patent: 4262342 (1981-04-01), Tuan
patent: 4274013 (1981-06-01), Clemons et al.
Kuo et al., "16-K RAM Built with Proven Process May Offer High Start-Up Reliability", Electronics, pp. 81-86; 5/13/76.

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