Integrated circuit load device

Details Integrated circuit load device Integrated circuit load device

Filed on

1985-11-20

Date issued

1987-02-03

Examiner

Carroll, J.

Other Related Categories

357 4, 357 6, 357 231, 357 41, 357 58, 357 59, H01L 2712, H01L 4902, H01L 2978, H01L 2702

Type

Patent

Status

active

Patent number

046411739

Description

ABSTRACT:
One embodiment of the present invention provides a polycrystalline silicon loading device occupying a minimum of surface area in an integrated circuit. A very thin layer of silicon nitride is formed on the surface of a heavily doped contact point in the integrated circuit. An undoped layer of polycrystalline silicon is then formed on the surface of this thin layer of silicon nitride. A thin layer of silicon nitride is then formed on the surface of the undoped polycrystalline silicon layer. Finally a heavily doped polycrystalline silicon layer for making contact to the loading device is formed on the surface of the second thin silicon nitride layer. Because the two thin silicon nitride layers are very thin, tunneling current through the silicon nitride layers begins at a fairly low threshold level. After tunneling occurs, the main resistance element of the load device is the undoped polycrystalline silicon. The silicon nitride layers prevent the diffusion of dopants into the undoped polycrystalline silicon layer thereby maintaining the integrity of the resistive characteristics of the undoped polycrystalline silicon. Using this technique a load approximately 1 micron squared using present lithographic techniques may be fabricated.

REFERENCES:
patent: 4212020 (1980-08-01), Yariv et al.
patent: 4403239 (1983-09-01), Yamazaki
patent: 4502208 (1985-03-01), McPherson

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