Self-aligned lateral bipolar transistors

Details Self-aligned lateral bipolar transistors Self-aligned lateral bipolar transistors

1985-08-05

1987-02-03

Edlow, Martin H.

357 34, 357 68, 357 71, H01L 2972

Patent

active

046411704

ABSTRACT:
An integrated circuit structure which includes small area lateral bipolar and method for making the same is described. A semiconductor body, such as a monocrystalline silicon wafer, having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction base region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical ohmic contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes electrical contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An electrical ohmic contact is made to the centrally located base region which contact is separated from the vertical conductive layers by the second insulating layer.

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Antipov, I., "Method for Making Lateral PNP Devices" IBM Tech. Disc. Bull., vol. 24, No. 3, 8/81, pp. 1745-1746.

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