Complex direct coupled transistor logic

Details Complex direct coupled transistor logic Complex direct coupled transistor logic

1984-07-02

1987-02-03

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 36, 357 46, 357 92, H03K 19082, H03K 19091, H01L 2704

Patent

active

046410473

ABSTRACT:
A logic circuit is provided having increased flexibility, increased package density over I2L circuits and improved noise immunity over ISL circuits. A first NPN multi-collector transistor has its collectors coupled wherein each provide an output signal, and a base connected to an input terminal and to the base of a second NPN transistor. The emitter of the second transistor is coupled to receive a first supply voltage, typically ground. The input terminal is coupled to a second supply voltage by a resistor. When monolithically integrated, the emitter and collector of the first and second transistor, respectively, share a common buried epitaxial layer that does not require contact with a metallization layer.

REFERENCES:
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patent: 3916218 (1975-10-01), Berger et al.
patent: 3956641 (1976-05-01), Berger et al.
patent: 4204130 (1980-05-01), Harris
patent: 4219828 (1980-08-01), Lardy et al.
patent: 4301382 (1981-11-01), Kameyana
patent: 4518874 (1985-05-01), Davis et al.

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