Multi-processor using shared buses

Details Multi-processor using shared buses Multi-processor using shared buses

1988-03-03

1989-02-07

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1340, G06F 1314, G06F 1516

Patent

active

048036170

ABSTRACT:
A multi-processor apparatus is disclosed which includes an array of separately addressable memory units and an array of separately addressable processors. A first unidirectional bus delivers data from a selected processor to a selected memory unit. A second unidirectional data bus delivers data from a selected memory unit to a selected processor. Arbitor circuits control the flow of data to these data buses.

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