Schottky gate field effect transistor and manufacturing method

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357 22, 357 89, 357 90, H01L 2948

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048035262

ABSTRACT:
In a GaAs field effect transistor of the invention, a gate layer is formed on a semi-insulative substrate. The gate layer is made of a conductive material forming a Schottky junction between the substrate and the gate layer. Source and drain regions are formed in the substrate to have a first conductivity type. Barrier layers are formed in the substrate to have a second conductivity type. The barrier layers are formed to surround the source and drain regions, and suppress a current component from leaking from the source and drain regions to the substrate when the field effect transistor is operative.

REFERENCES:
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patent: 4216038 (1980-08-01), Nishizawa et al.
patent: 4393578 (1983-07-01), Cady et al.
Patent Abstracts of Japan-vol. 8, No. 277 (E-285) [1714]-12-18[-84 & JP-A-59 147464 (ASAI).
Patents Abstracts of Japan, vol. 8, No. 277 (E-285) [1714], 18th Dec. 1984; & JP-A-59 147 464 (Nippon Denki K.K.)
IBM Technical Disclosure Bulletin, vol. 25, No. 5, Oct. 1982, p. 2373, New York, US; T. L. Andrade: "MESFET Device with Reduced Source and Drain Capacitance".
International Electron Devices Meeting, San Francisco, CA, US, 13th-15th Dec. 1982, pp. 718-721, IEEE, New York, US; S. Ogura et al: "A Half Micron MOSFET Using Double Implanted LDD".
Patents Abstracts of Japan, vol. 5, No. 171 (E-80) [843], 30th Oct. 1981; & JP-A-56 100 478 (Tokyo Shibaura Denki K.K.) 12-08-1981.
IBM Technical Disclosure Bulletin, vol. 26, No. 4, Sep. 1983, pp. 1988-1989, New York, US; C. F. Codella et al. "GaAs LDD E-MESFET for Ultra-High Speed Logic", FIG. 2.
The Institute of Applied Physics: A Draft Paper for '83 Spring National Meeting Lecture 7p-D-3, P457: Experimental Study Electrical Properties of Submicron Length Gate Self-Alignment Structured GaAs Fet.
The Institute of Electronics and Communication Engineers of Japan ED 84-86, pp. 1-6, "10ps Buried P-Layer Saint for GaAs LSIs".

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