MOS dynamic load circuit for switching high voltages and adapted

Details MOS dynamic load circuit for switching high voltages and adapted MOS dynamic load circuit for switching high voltages and adapted

1982-12-28

1986-04-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307453, 307481, 307246, 307577, 307264, H03K 1710, H03K 17693

Patent

active

045800677

ABSTRACT:
A dynamic load circuit (34) selectively applies a high voltage state to a circuit node (42). A clock signal is coupled to a first node (54) and the inverse of the clock signal is coupled to a second node (60). Isolation transistors (50, 70) are controlled by the voltage level at the circuit node (42) to isolate the clock signals from the first and second nodes (54, 60) when the circuit node (42) is at a low voltage state. A high voltage signal V.sub.pp is coupled through a transistor (58) to the first node (54). The voltage at the first node (54) is coupled through a transistor (56) to the circuit node (42). The circuit node (42) is further coupled through transistors (62, 64) to the second node (60). The application of the alternating positive transistions of the clock and inverse clock signal cause the circuit (34) to apply a progressively increasing voltage to the circuit node (42). The dynamic load circuit (34) functions even if the threshold voltages of the high voltage transistors therein are almost as high as the supply voltage.

REFERENCES:
patent: 3909627 (1975-09-01), Mizuno
patent: 3938108 (1976-02-01), Salsbury et al.
patent: 4322675 (1982-03-01), Lee et al.
patent: 4352996 (1982-10-01), White, Jr.
patent: 4354123 (1982-10-01), Eaton, Jr.
patent: 4451748 (1984-05-01), Amrany

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